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www.irf.com 1 afl50xxd series description 30v to 80v input range 5v, 12v, and 15v outputs available high power density - up to 70w/in 3 up to 100w output power parallel operation with stress and current sharing low profile (0.380") seam welded package ceramic feedthru copper core pins high efficiency - to 85% full military temperature range continuous short circuit and overload protection output voltage trim primary and secondary referenced inhibit functions line rejection > 40db - dc to 50khz external synchronization port fault tolerant design single output versions available standard microcircuit drawings available features 50v input, dual output hybrid-high reliability dc/dc converter the afl series of dc/dc converters feature high power density with no derating over the full military temperature range. this series is offered as part of a complete family of converters providing single and dual output voltages and operating from nominal +28v, +50v, +120v or +270 v inputs with output power ranging from 80w to 120w. for applications requiring higher output power, individual converters can be operated in parallel. the internal current sharing circuits assure equal current distribution among the paralleled converters. this series incorporates international rectifier?s proprietary magnetic pulse feedback technology providing optimum dynamic line and load regulation response. this feedback system samples the output voltage at the pulse width modulator fixed clock frequency, nominally 550 khz. multiple converters can be synchronized to a system clock in the 500khz to 700khz range or to the synchronization output of one converter. undervoltage lockout, primary and secondary referenced inhibit, soft- start and load fault protection are provided on all models. manufactured in a facility fully qualified to mil-prf- 38534, these converters are fabricated utilizing dscc qualified processes. for available screening options, refer to device screening table in the data sheet. variations in electrical, mechanical and screening can be accommodated. contact ir santa clara for special requirements. these converters are hermetically packaged in two enclosure variations, utilizing copper core pins to minimize resistive dc losses. three lead styles are available, each fabricated with international rectifier?s rugged ceramic lead-to-package seal assuring long term hermeticity in the most harsh environments. afl pd - 94456b
2 www.irf.com afl50xxd series specifications static characteristics -55c < t case < +125c, 30v < v in < 80v unless otherwise specified. for notes to specifications, refer to page 4 input voltage -0.5v to +50vdc soldering temperature 300c for 10 seconds operating case temperature -55c to +125c storage case temperature -65c to +135c absolute maximum ratings parameter group a subgroups test conditions min nom max unit input voltage note 6 30 50 80 v output voltage afl5005d afl5012d afl5015d afl5005d afl5012d afl5015d 1 1 1 1 1 1 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 v in = 50 volts, 100% load positive output negative output positive output negative output positive output negative output positive output negative output positive output negative output positive output negative output 4.95 -5.05 11.88 -12.12 14.85 -15.15 4.90 -5.10 11.76 -12.24 14.70 -15.30 5.00 -5.00 12.00 -12.00 15.00 -15.00 5.05 -4.95 12.12 -11.88 15.15 -14.85 5.10 -4.90 12.24 -11.76 15.30 -14.70 v output current afl5005d afl5012d afl5015d v in = 30, 50, 80 volts - notes 6, 11 either output either output either output 12.8 6.4 5.3 a output power afl5005d afl5012d afl5015d total of both outputs. notes 6,11 80 96 100 w maximum capacitive load each output note 1 10,000 f output voltage temperature coefficient v in = 50 volts, 100% load - notes 1, 6 -0.015 +0.015 %/c output voltage regulation line load cross afl5005d afl5012d afl5015d 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 note 10 no load, 50% load, 100% load v in = 30, 50, 80 volts. v in = 30, 50, 80 volts. note 12 positive output negative output positive output negative output positive output negative output -0.5 -1.0 -1.0 -8.0 -1.0 -5.0 -1.0 -5.0 +0.5 +1.0 +1.0 +8.0 +1.0 +5.0 +1.0 +5.0 %
www.irf.com 3 afl50xxd series static characteristics (continued) for notes to specifications, refer to page 4 parameter group a subgroups test conditions min nom max unit output ripple voltage afl5005d afl5012d afl5015d 1, 2, 3 1, 2, 3 1, 2, 3 v in = 30, 50, 80 volts, 100% load, bw = 10mhz 60 80 80 mv pp input current no load inhibit 1 inhibit 2 1 2, 3 1, 2, 3 1, 2, 3 v in = 50 volts i out = 0 pin 4 shorted to pin 2 pin 12 shorted to pin 8 50 60 5.0 5.0 ma input ripple current afl5005d afl5012d afl5015d 1, 2, 3 1, 2, 3 1, 2, 3 v in = 50 volts, 100% load 60 60 60 ma pp current limit point expressed as a percentage of full rated load 1 2 3 v out = 90% v nom , current split equall y on positive and ne g ative outputs. note 5 115 105 125 125 115 140 % load faultpower dissipation overload or short circuit 1, 2, 3 v in = 50 volts 32 w efficiency afl5005d afl5012d afl5015d 1, 2, 3 1, 2, 3 1, 2, 3 v in = 50 volts, 100% load 78 80 81 81 84 85 % enable inputs (inhibit function) converter off sink current converter on sink current 1, 2, 3 1, 2, 3 logical low on pin 4 or pin 12 note 1 logical high on pin 4 and pin 12 - note 9 note 1 -0.5 2.0 0.8 100 50 100 v a v a switching frequency 1, 2, 3 500 550 600 khz synchronization input frequency range pulse amplitude, hi pulse amplitude, lo pulse rise time pulse duty cycle 1, 2, 3 1, 2, 3 1, 2, 3 note 1 note 1 500 2.0 -0.5 20 700 10 0.8 100 80 khz v v ns % isolation 1 input to output or any pin to case (except pin 3). test @ 500vdc 100 m ? device weight slight variations with case style 85 g mtbf mil-hdbk-217f, aif @ t c = 40c 300 khrs
4 www.irf.com afl50xxd series dynamic characteristics -55c < t case < +125c, v in =50v unless otherwise specified. notes to specifications: parameter group a subgroups test conditions min nom max unit load transient response afl5005d amplitude either output recovery amplitude recovery afl5012d amplitude either output recovery amplitude recovery afl5015d amplitude either output recovery amplitude recovery 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 note 2, 8 load step 50% ? 100% load step 10% ? 50% 10% ? 50% 50% ? 10% load step 50% ? 100% load step 10% ? 50% 10% ? 50% 50% ? 10% load step 50% ? 100% load step 10% ? 50% 10% ? 50% 50% ? 10% -450 -450 -750 -750 -750 -750 450 200 450 200 400 750 200 750 200 400 750 200 750 200 400 mv s mv s s mv s mv s s mv s mv s s line transient response amplitude recovery note 1, 2, 3 v in step = 30 ? 80 volts -500 500 500 mv s turn-on characteristics overshoot delay 4, 5, 6 4, 5, 6 note 4 enable 1, 2 on. (pins 4, 12 high or open) 50 75 250 120 mv ms load fault recovery same as turn on characteristics. line rejection mil-std-461d, cs101, 30hz to 50khz note 1 40 50 db 1. parameters not 100% tested but are guaranteed to the limits specified in the table. 2. recovery time is measured from the initiation of the transient to where v out has returned to within 1% of v out at 50% load. 3. line transient transition time 100 s. 4. turn-on delay is measured with an input voltage rise time of between 100v and 500v per millisecond. 5. current limit point is that condition of excess load causing output voltage to drop to 90% of nominal. 6. parameter verified as part of another test. 7. all electrical tests are performed with the remote sense leads connected to the output leads at the load. 8. load transient transition time 10 s. 9. enable inputs internally pulled high. nominal open circuit voltage 4.0vdc. 10. load current split equally between +v out and -v out . 11. output load must be distributed so that a minimum of 20% of the total output power is being provided by one of the outputs. 12. cross regulation measured with load on tested output at 20% while changing the load on other output from 20% to 80%.
www.irf.com 5 afl50xxd series block diagram figure i. dual output figure ii. enable input equivalent circuit circuit operation and application information inhibiting converter output (enable) as an alternative to application and removal of the dc volt- age to the input, the user can control the converter output by providing ttl compatible, positive logic signals to either of two enable pins (pin 4 or 12). the distinction between these two signal ports is that enable 1 (pin 4) is referenced to the input return (pin 2) while enable 2 (pin 12) is referenced to the output return (pin 8). thus, the user has access to an inhibit function on either side of the isolation barrier. each port is internally pulled ?high? so that when not used, an open con- nection on both enable pins permits normal converter opera- tion. when their use is desired, a logical ?low? on either port will shut the converter down. the afl series of converters employ a forward switched mode converter topology. (refer to figure i.) operation of the device is initiated when a dc voltage whose magnitude is within the specified input limits is applied between pins 1 and 2. if pins 4 and 12 are enabled (at a logical 1 or open) the primary bias supply will begin generating a regulated house- keeping voltage bringing the circuitry on the primary side of the converter to life. two power mosfets used to chop the dc input voltage into a high frequency square wave, apply this chopped voltage to the power transformer. as this switch- ing is initiated, a voltage is impressed on a second winding of the power transformer which is then rectified and applied to the primary bias supply. when this occurs, the input voltage is excluded from the bias voltage generator and the primary bias voltage becomes internally generated. the switched voltage impressed on the secondary output transformer windings is rectified and filtered to provide the positive and negative converter output voltages. an error amplifier on the secondary side compares the positive out- put voltage to a precision reference and generates an error signal proportional to the difference. this error signal is mag- netically coupled through the feedback transformer into the control section of the converter varying the pulse width of the square wave signal driving the mosfets, narrowing the pulse width if the output voltage is too high and widening it if it is too low. these pulse width variations provide the neces- sary corrections to maintain the magnitude of output voltage within its? specified limits. because the primary and secondary sides are coupled by magnetic elements, full isolation from input to output is achieved. disable 100k 290k 180k 1n4148 2n3904 +5.6 v pin 4 or pin 12 pin 2 or pin 8 although incorporating several sophisticated and useful ancillary features, basic operation of the afl50xxd series can be initiated by simply applying an input voltage to pins 1 and 2 and connecting the appropriate loads between pins 7, 8, and 9. of course, operation of anyconverter with high power density should not be attempted before secure at- tachment to an appropriate heat dissipator. (see thermal considerations, page 7) error amp & ref output filter input filter output return + input input return fb control 1 2 4 3 5 6 sync inpu t current sense enable 2 share share amplifier 7 11 10 9 12 8 + output sync output enable 1 case primary bias supply - output output voltage trim filter output
6 www.irf.com afl50xxd series figure iii. preferred connection for parallel operation synchronization of multiple converters parallel operation-current and stress sharing internally, these ports differ slightly in their function. in use, a low on enable 1 completely shuts down all circuits in the converter, while a low on enable 2 shuts down the secondary side while altering the controller duty cycle to near zero. externally, the use of either port is transparent to the user save for minor differences in idle current. (see specification table). when operating multiple converters, system requirements often dictate operation of the converters at a common frequency. to accommodate this requirement, the afl series converters provide both a synchronization input and output. the sync input port permits synchronization of an afl converter to any compatible external frequency source operating between 500khz and 700khz. this input signal should be referenced to the input return and have a 10% to 90% duty cycle. compatibility requires transition times less than 100ns, maximum low level of +0.8v and a minimum high level of +2.0v. the sync output of another converter which has been designated as the master oscillator provides a convenient frequency source for this mode of operation. when external synchronization is not required, the sync in pin should be left unconnected thereby permitting the converter to operate at its? own internally set frequency. the sync output signal is a continuous pulse train set at 550 50khz, with a duty cycle of 15 5.0%. this signal is referenced to the input return and has been tailored to be compatible with the afl sync input port. transition times are less than 100ns and the low level output impedance is less than 50 ? . this signal is active when the dc input voltage is within the specified operating range and the converter is not inhibited. the sync output has adequate drive reserve to synchronize at least five additional converters. a typical connection is illustrated in figure iii. power input (other converters) share bus 1 6 afl 7 12 - output enable 2 + output return trim share vin rtn case enable 1 sync out sync in 1 6 afl 7 12 - output enable 2 + output return trim share vin rtn case enable 1 sync out sync in 1 6 afl 7 12 - output enable 2 + output return trim share vin rtn case enable 1 sync out sync in optional synchronization connection to positive load to negative load figure iii. illustrates the preferred connection scheme for operation of a set of afl converters with outputs operating in parallel. use of this connection permits equal current sharing among the members of a set whose load current exceeds the capacity of an individual afl. an important feature of the afl series operating in the parallel mode is that in addition to sharing the current, the stress induced by temperature will also be shared. thus if one member of a paralleled set is operating at a higher case temperature, the current it provides to the load will be reduced as compenstionfor the temperature induced stress on that device.
www.irf.com 7 afl50xxd series a conservative aid to estimating the total heat sink surface area (a heat sink ) required to set the maximum case temperature rise ( ? t) above ambient temperature is given by the following expression: a heat sink ? ? ? ? ? ? ? ? ? t p 80 30 085 143 . . . where ? t pp eff out = ==? ? ? ? ? ? ? case temperature rise above ambient device dissipation in watts 1 1 ? t = 85 - 25 = 60c and the required heat sink area is if the worst case full load efficiency for this device is 83% @ 100w; then the power dissipation at full load is given by because of the incorporation of many innovative technological concepts, the afl series of converters is capable of providing very high output power from a package of very small volume. these magnitudes of power density can only be obtained by combining high circuit efficiency with effective methods of heat removal from the die junctions. this requirement has been effectively addressed inside the device; but when operating at maximum loads, a significant amount of heat will be generated and this heat must be conducted away from the case. to maintain the case temperature at or below the specified maximum of 125c, this heat must be transferred by conduction to an appropriate heat dissipater held in intimate contact with the converter base-plate. when operating in the shared mode, it is important that symmetry of connection be maintained as an assurance of optimum load sharing performance. thus, converter outputs should be connected to the load with equal lengths of wire of the same gauge and sense leads from each converter should be connected to a common physical point, preferably at the load along with the converter output and return leads. all converters in a paralleled set must have their share pins connected together. this arrangement is diagrammatically illustrated in figure iii. showing the outputs and return pins connected at a star point which is located close as possible to the load. as a consequence of the topology utilized in the current sharing circuit, the share pin may be used for other functions. for applications requiring only a single converter, the voltage appearing on the share pin may be used as a ?current monitor?. the share pin open circuit voltage is nominally +1.00v at no load and increases linearly with increasing output current to +2.20v at full load. note that the current we refer to here is the total device output current, that is, the sum of the positive and negative output currents. 1 sil-pad is a registered trade mark of bergquist, minneapolis, mn thermal considerations since the effectiveness of this heat transfer is dependent on the intimacy of the baseplate/heatsink interface, it is strongly recommended that a high thermal conductivity heat transferring medium is inserted between the baseplate and heatsink. the material most frequently utilized at the factory during all testing and burn-in processes is sold under the trade name of sil-pad ? 400 1 . this particular product is an insulator but electrically conductive versions are also available. use of these materials assures maximum surface contact with the heat dissipater thereby compensating for any minor surface variations. while other available types of heat conductive materials and thermal compounds provide similareffectiveness, these alternatives are often less convenient and can be somewhat messy to use. as an example, it is desired to maintain the case temperature of an afl5015d at +85c while operating in an open area whose ambient temperature is held at a constant +25c; then thus, a total heat sink surface area (including fins, if any) of 56 in 2 in this example, would limit case rise to 60c above ambient. a flat aluminum plate, 0.25" thick and of approximate dimension 4" by 7" (28 in 2 per side) would suffice for this application in a still air environment. note that to meet the criteria in this example, both sides of the plate require unrestricted exposure to the +25c ambient air. () p =? ? ? ? ? ? ? ? =? = 100 1 83 1 100 0 205 20 5 . ..w a = 60 80 20.5 in heat sink 0.85 ? ? ? ? ? ? ? ?= ? 143 2 30 563 . ..
8 www.irf.com afl50xxd series input filter undervoltage lockout the afl50xxd series converters incorporate a single stage lc input filter whose elements dominate the input load impedance characteristic during the turn-on. the input circuit is as shown in figure iv. figure iv. input filter circuit output voltage adjust by use of the trim pin (10), the magnitude of output voltages can be adjusted over a limited range in either a positive or negative direction. connecting a resistor between the trim pin and either the output return or the positive output will raise or lower the magnitude of output voltage. the span of output voltage magnitude is restricted to the limits shown in table i. figure v. connection for v out adjustment connect radj to + to increase, - to decrease. table i. output voltage trim values and limits afl5005d afl5012d afl5015d v out r ad j v out r ad j v out r ad j 5.5 0 12.5 0 15.5 0 5.4 12.5k 12.4 47.5k 15.4 62.5k 5.3 33.3k 12.3 127k 15.3 167k 5.2 75k 12.2 285k 15.2 375k 5.1 200k 12.1 760k 15.1 1.0m 5.0 12.0 15.0 4.9 190k 11.7 975k 14.6 1.2m 4.8 65k 11.3 288k 14.0 325k 4.7 23k 10.8 72.9k 13.5 117k 4.6 2.5k 10.6 29.9k 13.0 12.5k 4.583 0 10.417 0 12.917 0 note that the nominal magnitude of output voltage resides in the middle of the table and the corresponding resistor value is set to . to set the magnitude above nominal, the adjust resistor is connected to output return. to set the magnitude below nominal, the adjust resistor is connected to the positive output. (refer to figure v.) for output voltage settings that are within the limits, but between those presented in table i, it is suggested that the resistor values be determined empirically by selection or by use of a variable resistor. the value thus determined can then be replaced with a good quality fixed resistor for permanent installation. when use of the trim feature is elected, the user should be aware that the temperature performance of the converter output voltage will be affected by the temperature performance of the resistor selected as the adjustment element and therefore, the user is advised to employ resistors with an very small temperature coefficient of resistance. 0.75h pin 1 pin 2 2.7fd a minimum voltage is required at the input of the converter to initiate operation. this voltage is set to 26.5 1.5v. to preclude the possibility of noise or other variations at the input falsely initiating and halting converter operation, a hysteresis of approximately 2.0v is incorporated in this circuit. thus if the input voltage droops to 24.5 1.5v, the converter will shut down and remain inoperative until the input voltage returns to 25v. enable 2 share trim - vout return + vout to loads r adj afl50xxd 7 12 + -
www.irf.com 9 afl50xxd series mechanical outlines case x case w pin variation of case y 1.260 1.500 2.500 2.760 3.000 ? 0.128 0.250 1.000 ref 0.200 typ non-cum 0.050 0.220 pin ? 0.040 0.238 max 0.380 max 2.975 max 1 6 7 12 0.050 0.220 0.250 1.000 pin ? 0.040 0.525 0.380 max 2.800 0.42 case y case z pin variation of case y 1.500 1.750 2.500 0.25 typ 1.150 0.050 0.220 1 6 7 12 1.750 0.375 2.00 0.250 1.000 ref 0.200 typ non-cum pin ? 0.040 0.300 ? 0.140 0.238 max 0.380 max 2.975 max 0.050 0.220 0.250 1.000 ref pin ? 0.040 0.525 0.380 max 2.800 0.36 ber yllia w arning : these converters are hermetically sealed; however they contain beo substrates and should not be ground or subjected to any o ther operations including exposure to acids, which may produce beryllium dust or fumes containing beryllium tolerances, unless otherwise specified: .xx = 0.010 .xxx = 0.005
10 www.irf.com afl50xxd series standard microcircuit drawing equivalence table pin designation pin # designation 1 + input 2 input return 3 case ground 4 enable 1 5 sync output 6 sync input 7 + output 8 output return 9 - output 10 output voltage trim 11 share 12 enable 2 standard microcircuit ir standard drawing number part number 5962-02563 afl5005d 5962-02564 afl5012d 5962-02565 afl5015d
www.irf.com 11 afl50xxd series part numbering notes: best commercial practice sample tests at low and high temperatures -55c to +105c for ahe, ato, atw world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 322 3331 ir santa clara: 2270 martin av., santa clara, california 95050, tel: (408) 727-0500 visit us at www.irf.com for sales contact information . data and specifications subject to change without notice. 12/2006 device screening requirement mil-std-883 method no suffix es hb ch temperature range -20c to +85c -55c to +125c -55c to +125c -55c to +125c element evaluation mil-prf-38534 n/a n/a n/a class h non-destructive bond pull internal visual 2017 yes yes yes temperature cycle 1010 n/a cond b cond c cond c constant acceleration 2001, y1 axis n/a 500 gs 3000 gs 3000 gs pind 2020 n/a n/a n/a n/a burn-in 1015 n/a 48 hrs@hi temp 160 hrs@125c 160 hrs@125c final electrical mil-prf-38534 25c 25c -55c, +25c, -55c, +25c, ( group a ) & specification +125c +125c pda mil-prf-38534 n/a n/a n/a 10% seal, fine and gross 1014 cond a cond a, c cond a, c cond a, c radiographic 2012 n/a n/a n/a n/a external visual 2009 yes yes yes n/a n/a 2023 n/a n/a afl 50 05 d x /ch model input voltage 28 = 28v 50 = 50v 120 = 120v 270 = 270v output voltage output d = dual case style w, x, y, z screening level (please refer to screening table) no suffix, es, hb, ch 05 = 5v 12 = 12v 15 = 15v

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